There is a need in the integrated circuit art for obtaining increasingly smaller devices without sacrificing device performance. The small device size requires small device regions, precise and accurate alignment between regions and minimization of parasitic resistances and capacitances. Device size can be reduced by putting more reliance on fine line lithography, but as discussed below, it becomes impractical or impossible to continue to reduce feature size and achieve the required greater increase in alignment accuracy. As lithography is pushed to the limit, yield and production throughput decrease.
Four governing performance parameters of a photolithographic system are limit-of-resolution, Lr, level-to-level alignment accuracy, and depth-of-focus, and throughput. For purposes of this discussion, limit-of-resolution, level-to-level alignment, and depth-of-focus are physically constrained parameters.
Typical photolithographic techniques are limited by physical constraints of the photolithographic system involving actinic radiation wavelength, λ, and geometrical configurations of the projection system optics. According to Rayleigh's criterion,
      L    r    =            0.61      ⁢                          ⁢      λ        NA  where NA is the numerical aperture of the optical system and is defined as NA=n sin α, where n is the index of refraction of the medium which the radiation traverses (usually air for this application, so n≅1) and α is a half-angle of the divergence of the actinic radiation. For example, using deep ultraviolet illumination (DUV) with λ=193 nm, and NA=0.7, the lower limit of resolution is 168 nanometers (1680 Å). Techniques such as phase-shifted masks can extend this limit downward, but photomasks required in this technique are extremely expensive. This expense becomes greatly compounded with a realization that an advanced semiconductor process may employ more than 25 photomasks.
Along witch the limit-of-resolution, the second parameter, level-to-level alignment accuracy becomes more critical as feature sizes on photomasks decrease and a number of total photomasks increases. For example, if photomask alignment by itself causes a reduction in device yield to 95% per layer, then 25 layers of photomask translates to a total device yield of 0.9525=0.28 or 28% yield (assuming independent errors). Therefore, a more complicated mask, such a phase-shifted mask is not only more expensive but device yield can suffer dramatically.
Further, although the numerical aperture of the photolithographic system may be increased to lower the limit-of-resolution, the third parameter, depth-of-focus, will suffer as a result. Depth-of-focus is inversely proportional to NA2. Therefore, as NA increases, limit-of-resolution decreases but depth-of-focus decreases more rapidly. The reduced depth-of-focus makes accurate focusing more difficult especially on non-planar features such as “Manhattan Geometries” becoming increasingly popular in advanced semiconductor devices.
Recently, techniques have been developed to make smaller scale transistors and related devices. One such method of making transistors is described in U.S. Pat. No. 5,067,022 to Zdebel et al., assigned to Motorola, Inc. Here, a process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. However, that process is still limited by requiring large implant areas. For example, a bipolar transistor base region still requires photomasks and photolithographic techniques for its production. An integrated circuit device, or even a single transistor or other electronic device fabricated by this method cannot be scaled down beyond a given point. Further, a high base-emitter capacitance resulting from use of this method severely affects device performance.
Additionally, in a conventional method for fabricating a bipolar device, an emitter window is directly opened without some means of providing an etch stop. This overetch produces a damaged region in the silicon and may result in excessive consumption of silicon underlying the contact. Further, formation of an oxide spacer without an etch stop presents manufacturing difficulties as timing and other recipe tolerances become overly stringent.
For at least the aforementioned reasons, integrated circuit manufacturers have been unable to sufficiently reduce a size of electronic devices while still maintaining high performance. In view of the desire for integrated circuits having higher device counts, smaller device sizes, and greater circuit performance, a need continues to exist for an improved process to manufacture the required devices without resorting to unrealistic and expensive photolithography requirements.
Accordingly, what is needed is a way to provide an improved process and structure for fabricating integrated circuit devices. Such a structure for producing integrated circuit devices would have devices with a reduced size with reasonable photolithographic tolerances.